Cache Optimization for H.264/AVC Motion Compensation

Sangyong YOON  Soo-Ik CHAE  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.12   pp.2902-2905
Publication Date: 2008/12/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.12.2902
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Image Processing and Video Processing
cache,  H.264,  motion compensation,  memory bandwidth,  DDR SDRAM,  

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In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.