A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Takayuki ONISHI  Ken NAKAMURA  Takeshi YOSHITOME  Jiro NAGANUMA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.12   pp.2862-2867
Publication Date: 2008/12/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.12.2862
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Image Processing and Video Processing
Keyword: 
super high-resolution video,  multiplexing,  codec LSI,  

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Summary: 
This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.