Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

Thomas Edison YU  Tomokazu YONEDA  Krishnendu CHAKRABARTY  Hideo FUJIWARA  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.10   pp.2440-2448
Publication Date: 2008/10/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.10.2440
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
SoC testing,  test architecture design,  test scheduling,  thermal constraint,  

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Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.