A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

Hong-Ming SHIEH  Jin-Fu LI  

IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.10   pp.2428-2434
Publication Date: 2008/10/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.10.2428
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
system-on-chip,  test,  compression,  multi-code compression,  decompression,  

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With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small--only about 3498 µm2 based on TSMC 0.18 µm standard cell technology.