Deadzone-Minimized Systematic Offset-Free Phase Detectors

Young-Sang KIM
Yunjae SUH
Hong-June PARK
Jae-Yoon SIM

IEICE TRANSACTIONS on Electronics   Vol.E91-C    No.9    pp.1525-1528
Publication Date: 2008/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.9.1525
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
phase detector,  phase offset,  deadzone,  multiphase generation,  delay-locked loop,  phase-locked loop,  

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Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.