Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration

Hirofumi SHINOHARA  Koji NII  Hidetoshi ONODERA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.9   pp.1488-1500
Publication Date: 2008/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.9.1488
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
SRAM,  memory cell,  static noise margin,  SNM,  variability,  

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Summary: 
An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.