IEICE Trans - A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

Hsin-Hung OU
Bin-Da LIU
Soon-Jyh CHANG

Publication
IEICE TRANSACTIONS on Electronics Vol.E91-C No.9 pp.1480-1487
Publication Date: 2008/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.9.1480
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword:
switched-opamp, low-voltage, high-speed, sample-and-hold, double-sampling,

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Summary:
This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3 dB up to 250 MSample/s and a 0.8 V_PP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.