Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

Takeshi KUMAKI
Masakatsu ISHIZAKI
Tetsushi KOIDE
Takayuki GYOHTEN
Hideyuki NODA
Katsumi DOSAKA
Kazutami ARIMOTO
Kazunori SAITO

IEICE TRANSACTIONS on Electronics   Vol.E91-C    No.9    pp.1409-1418
Publication Date: 2008/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.9.1409
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
content addressable memory,  CAM,  matrix-processing architecture,  SIMD,  bit-serial and word-parallel,  table-lookup coding,  DCT,  Huffman coding,  JPEG,  

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This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.