Ultra Dependable Processor

Shuichi SAKAI  Masahiro GOSHIMA  Hidetsugu IRIE  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.9   pp.1386-1393
Publication Date: 2008/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.9.1386
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
microprocessor architecture,  dependable computing,  attacks,  faults,  errors,  failures,  soft errors,  timing errors,  tamper resistance,  information flow,  injection attack,  dependability manager,  

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Summary: 
This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.