Accurate Modeling Method for Cu Interconnect

Kenta YAMADA  Hiroshi KITAHARA  Yoshihiko ASAI  Hideo SAKAMOTO  Norio OKADA  Makoto YASUDA  Noriaki ODA  Michio SAKURAI  Masayuki HIROI  Toshiyuki TAKEWAKI  Sadayuki OHNISHI  Manabu IGUCHI  Hiroyasu MINDA  Mieko SUZUKI  

IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.6   pp.968-977
Publication Date: 2008/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.6.968
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Cu,  interconnect,  cross-section,  modeling,  

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This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15 µm CMOS using this method and confirmed that 10% τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90 nm, 65 nm and 55 nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.