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Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
Kouji ICHIKAWA Yuki TAKAHASHI Yukihiko SAKURAI Takahiro TSUDA Isao IWASE Makoto NAGATA
IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
integrated circuit, electro magnetic interference, on-chip monitor, immunity,
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Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.