Techniques for Digitally Assisted Pipeline A/D Converters


IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.6   pp.829-836
Publication Date: 2008/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.6.829
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
pipeline ADC,  capacitor mismatch,  digital calibration,  background calibration,  

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This paper reviews techniques for digitally assisted pipeline ADCs. Errors of pipeline ADCs originated by capacitor mismatch, finite amplifier gain, incomplete settling and offset can be corrected in digital-domain foreground or background calibrations. In foreground calibrations, the errors are measured by reconfiguration of the building blocks of pipeline ADC or using an INL plot without reconfiguration. In background calibrations, the errors are measured with random signal and continuously corrected while simultaneously performing the normal A/D conversions. Techniques for measuring and correcting the errors at foreground and background are reviewed and a unified approach to the description of the principle of background calibration of gain errors is presented.