Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

Jang Gn YUN  Il Han PARK  Seongjae CHO  Jung Hoon LEE  Doo-Hyun KIM  Gil Sung LEE  Yoon KIM  Jong Duk LEE  Byung-Gook PARK  

IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.5   pp.742-746
Publication Date: 2008/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.5.742
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
2-bit recessed channel memory,  lifted-charge trapping node (L-CTN) scheme,  short channel effect (SCE),  second bit effect (SBE),  bottom-side effect (BSE),  VTH window,  

Full Text: PDF>>
Buy this Article

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).