Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Seongjae CHO  Il Han PARK  Jung Hoon LEE  Jang-Gn YUN  Doo-Hyun KIM  Jong Duk LEE  Hyungcheol SHIN  Byung-Gook PARK  

IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.5   pp.731-735
Publication Date: 2008/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.5.731
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
memory array,  electrical interference,  3-D memory device,  read operation,  PCI (paired cell interference),  

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Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.