Stress Effect Analysis for PD SOI pMOSFETs with Undoped-Si0.88Ge0.12 Heterostructure Channel

Sang-Sik CHOI  A-Ram CHOI  Jae-Yeon KIM  Jeon-Wook YANG  Yong-Woo HWANG  Tae-Hyun HAN  Deok Ho CHO  Kyu-Hwan SHIM  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.5   pp.716-720
Publication Date: 2008/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.5.716
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
SiGe,  MOSFET,  PD SOI,  stress effect,  

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Summary: 
The stress effect of SiGe p-type metal oxide semiconductor field effect transistors (MOSFETs) has been investigated to compare their properties associated with the Si0.88Ge0.12/Si epi channels grown on the Si bulk and partially depleted silicon on insulator (PD SOI) substrates. The stress-induced changes in the subthreshold slope and the drain induced barrier lowering were observed small in the SiGe PD SOI in comparison to in the SiGe bulk. Likewise the threshold voltage shift monitored as a function of hot carrier stress time presented excellent stability than in the SiGe PD SOI. Therefore, simply in terms of dc properties, the SiGe PD SOI looks more immune from electrical stresses than the SiGe bulk. However, the 1/f noise properties revealed that the hot carrier stress could introduce lots of generation-recombination noise sources in the SiGe PD SOI. The quality control of oxide-silicon in SOI structures is essential to minimize a possible surge of 1/f noise level due to the hot carrier injection. In order to improve dc and rf performance simultaneously, it is very important to grow the SiGe channels on high quality SOI substrates.