Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis

Masakazu AOKI  Shin-ichi OHKAWA  Hiroo MASUDA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.4   pp.647-654
Publication Date: 2008/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.4.647
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
modeling transistor variations,  within-die variation,  statistical analysis for transistor parameters,  SRAM cell sensitivity analysis,  process window for SRAM cell operation,  

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Summary: 
Random variations in Id-Vg characteristics of MOS transistors in an LSI chip are shown to be concisely characterized by using only 3 transistor parameters (Vth, β0, vSAT) in the MOS level 3 SPICE model. Statistical analyses of the transistor parameters show that not only the threshold voltage variation, ΔVth, but also the current factor variation, Δβ0, independently induces Id-variation, and that Δβ0 is negatively correlated with the saturation velocity variation, ΔvSAT. Using these results, we have proposed a simple method that effectively takes the correlation between parameters into consideration when creating statistical model parameters for designing a circuit. Furthermore, we have proposed a sensitivity analysis methodology for estimating the process window of SRAM cell operation taking transistor variability into account. By applying the concise statistical model parameters to the sensitivity analysis, we are able to obtain valid process windows without the large volume of data-processing and long turnaround time associated with the Monte Carlo simulation. The process window was limited not only by ΔVth, but also by Δβ0 which enhanced the failure region in the process window by 20%.