Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network

Hyunjeong PARK  Hyungsoo KIM  Jun So PAK  Changwook YOON  Kyoungchoul KOO  Joungho KIM  

IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.4   pp.595-606
Publication Date: 2008/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.4.595
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electromagnetic Theory
co-modeling,  hierarchical power distribution network (PDN),  chip and package,  

Full Text: PDF>>
Buy this Article

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1 MHz to 3 GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.