Redundant Vias Insertion for Performance Enhancement in 3D ICs

Xu ZHANG  Xiaohong JIANG  Susumu HORIGUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.4   pp.571-580
Publication Date: 2008/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.4.571
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
3D IC,  redundant vias,  via placement,  delay,  signal integrity,  impedance matching,  

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Summary: 
Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65 nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.