Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling

Masanori HARIYAMA  Naoto YOKOYAMA  Michitaka KAMEYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.4   pp.479-486
Publication Date: 2008/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.4.479
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
stereo vision,  scheduling,  allocation,  

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This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.