Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems

Makoto SUGIHARA  Tohru ISHIHARA  Kazuaki MURAKAMI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.4   pp.410-417
Publication Date: 2008/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.4.410
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
single event upset,  SRAM,  DRAM,  reliability,  cache architecture,  task scheduling,  

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Summary: 
This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling approach achieved 47.7-99.9% less vulnerability than a conventional one.