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6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator
Yun-Jeong KIM Jong-Ho LEE Ja-Hyun KOO Kwang-Hyun BAEK Suki KIM
IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
comparator, flash ADC, high-speed ADC, interpolation,
Full Text: PDF(768.9KB)>>
In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm2. It is fabricated in 0.18-µm CMOS.