IEICE Trans - A 12 b 200 kS/s 0.52 mA 0.47 mm<SUP>2</SUP> Algorithmic A/D Converter for MEMS Applications

A 12 b 200 kS/s 0.52 mA 0.47 mm² Algorithmic A/D Converter for MEMS Applications

Young-Ju KIM  Hee-Cheol CHOI  Seung-Hoon LEE  Dongil "Dan" CHO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C    No.2    pp.206-212
Publication Date: 2008/02/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.2.206
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword:
algorithmic,  low power,  MEMS,  ADC,  CMOS,

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Summary:
This work describes a 12 b 200 kS/s 0.52 mA 0.47 mm² ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 kS/s and 10 kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 dB and 70 dB at all sampling frequencies up to 200 kS/s, respectively. The ADC occupies an active die area of 0.47 mm² and consumes 0.94 mW at 200 kS/s and 0.63 mW at 10 kS/s with a 1.8 V supply.