For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Low-Power Switched Current Memory Cell with CMOS-Type Configuration
Masashi KATO Nobuyuki TERADA Hirofumi OHATA Eisuke ARAI
IEICE TRANSACTIONS on Electronics
Publication Date: 2008/01/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
switched current, low-power, CMOS-type, memory cell,
Full Text: PDF>>
This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.