A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop

Xin CHEN  Jun YANG  Long-xing SHI  

IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.12   pp.1971-1975
Publication Date: 2008/12/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.12.1971
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
digitally controlled phase-locked loop (DCPLL),  frequency divider,  frequency search algorithm,  

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A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.