A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator

Chang-Kyung SEONG  Seung-Woo LEE  Woo-Young CHOI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E91-B   No.5   pp.1397-1402
Publication Date: 2008/05/01
Online ISSN: 1745-1345
DOI: 10.1093/ietcom/e91-b.5.1397
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Devices/Circuits for Communications
Keyword: 
burst-mode,  clock and data recovery circuit,  digital phase aligner,  phase interpolator,  

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Summary: 
We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-µm CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231-1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.