A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission

Masayuki MIYAMA  Yuusuke INOIE  Takafumi KASUGA  Ryouichi INADA  Masashi NAKAO  Yoshio MATSUDA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.8   pp.2025-2034
Publication Date: 2008/08/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.8.2025
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Signal Processing)
JPEG 2000,  EBCOT,  VLSI,  low delay,  image transmission,  

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This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18 µm process. The core area is 4.74.7 mm2 and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay.