IEICE Trans - Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

Masahiro KAMINAGA
Takashi WATANABE
Takashi ENDO
Toshio OKOCHI

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E91-A No.7 pp.1816-1819
Publication Date: 2008/07/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.7.1816
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Cryptography and Information Security
Keyword:
fault attack, hardware security,

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Summary:
This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.