VLSI Implementation of a Complete Pipeline MMSE Detector for a 44 MIMO-OFDM Receiver

Shingo YOSHIZAWA  Yasushi YAMAUCHI  Yoshikazu MIYANAGA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.7   pp.1757-1762
Publication Date: 2008/07/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.7.1757
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
wireless communications,  MIMO-OFDM,  MIMO detection,  MMSE,  

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Summary: 
This paper presents a VLSI architecture of MMSE detection in a 44 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.