A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of fOSC to VDD

Felix TIMISCHL  Takahiro INOUE  Akio TSUNEDA  Daisuke MASUNAGA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.2   pp.504-512
Publication Date: 2008/02/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.2.504
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
CMOS,  ring oscillator,  low power,  gm-booster,  VDD-dependency,  composite transistor,  figure of merit,  

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Summary: 
A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49 µW at fOSC=13.56 MHz. The sensitivity of fOSC to VDD is reduced to -0.02 at fOSC=13.56 MHz thanks to the use of composite high-impedance current sources.