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Area-Efficient Reconfigurable Architecture for Media Processing Yukio MITSUYAMA Kazuma TAKAHASHI Rintaro IMAI Masanori HASHIMOTO Takao ONOYE Isao SHIRAKAWA Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E91-A No.12 pp.3651-3662 Publication Date: 2008/12/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e91-a.12.3651 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: reconfigurable, media processing, multi-standard, area-efficiency, dynamic reconfiguration, Full Text: PDF(901.6KB)>>
Summary: An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1  1.4 mm2 in a 90 nm CMOS technology. | ||||||||||
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