IEICE Trans - Way-Scaling to Reduce Power of Cache with Delay Variation

Way-Scaling to Reduce Power of Cache with Delay Variation

Maziar GOUDARZI  Tadayuki MATSUMURA  Tohru ISHIHARA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A    No.12    pp.3576-3584
Publication Date: 2008/12/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.12.3576
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
leakage,  power reduction,  cache,  within-die variation,  delay variation,  way scaling,

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Summary:
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (V_th) and/or gate-oxide thickness (T_ox) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90 nm process, we show that choosing higher V_th, T_ox and adding one spare way to a 4-way 16 KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache power, gives up to 22.59% and 41.37% reduction of total energy respectively in L1 instruction- and L2 unified-cache with a negligible delay penalty, but without sacrificing cache capacity or timing-yield.