Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

Yoshinobu HIGAMI
Kewal K. SALUJA
Hiroshi TAKAHASHI
Shin-ya KOBAYASHI
Yuzo TAKAMATSU

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A    No.12    pp.3506-3513
Publication Date: 2008/12/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.12.3506
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulation,  test generation,  stuck-open faults,  stuck-at tests,  defect coverage,  

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Summary: 
Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that a test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.