Impact of Well Edge Proximity Effect on Timing

Toshiki KANAMOTO  Yasuhiro OGASAHARA  Keiko NATSUME  Kenji YAMAGUCHI  Hiroyuki AMISHIRO  Tetsuya WATANABE  Masanori HASHIMOTO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.12   pp.3461-3464
Publication Date: 2008/12/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.12.3461
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
well edge proximity effect,  WPE,  delay,  timing,  

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Summary: 
This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.