For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Impact of Well Edge Proximity Effect on Timing
Toshiki KANAMOTO Yasuhiro OGASAHARA Keiko NATSUME Kenji YAMAGUCHI Hiroyuki AMISHIRO Tetsuya WATANABE Masanori HASHIMOTO
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
well edge proximity effect, WPE, delay, timing,
Full Text: PDF(377.8KB)>>
This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.