Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology

Woo Joo KIM  Sun Young HWANG  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.11   pp.3297-3303
Publication Date: 2008/11/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.11.3297
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
network on chip,  hybrid network topology,  low-power algorithm,  job distribution,  

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Summary: 
This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.