Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method

K.G. SMITHA  A.P. VINOD  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.11   pp.3282-3292
Publication Date: 2008/11/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.11.3282
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
Keyword: 
low power,  low complexity,  higher order FIR filters,  common subexpression elimination,  

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Summary: 
The complexity of Finite Impulse Response (FIR) filters is mainly dominated by the number of adders (subtractors) used to implement the coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) method based on Canonic Signed Digit (CSD) representation considerably reduces the number of adders in coefficient multipliers. Recently, a binary-based CSE (BSE) technique was proposed, which produced better reduction of adders compared to the CSD-based CSE. In this paper, we propose a new 4-bit binary representation-based CSE (BCSE-4) method which employs 4-bit Common Subexpressions (CSs) for implementing higher order low-power FIR filters. The proposed BCSE-4 offers better reduction of adders by eliminating the redundant 4-bit CSs that exist in the binary representation of filter coefficients. The reduction of adders is achieved with a small increase in critical path length of filter coefficient multipliers. Design examples show that our BCSE-4 gives an average power consumption reduction of 5.2% and 6.1% over the best known CSE method (BSE, NR-SCSE) respectively, when synthesized with TSMC-0.18 µm technology. We show that our BCSE-4 offers an overall adder reduction of 6.5% compared to BSE without any increase in critical path length of filter coefficient multipliers.