For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation
Chia Yee OOI Thomas CLOUQUEUR Hideo FUJIWARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Complexity Theory
easily testable, stuck-at faults, path delay faults, test generation complexity,
Full Text: PDF>>
In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τk-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.