Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation

Yukinori SATO  Ken-ichi SUZUKI  Tadao NAKAMURA  

IEICE TRANSACTIONS on Information and Systems   Vol.E90-D    No.3    pp.627-636
Publication Date: 2007/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e90-d.3.627
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: VLSI Systems
clustered architecture,  partitioned register files,  non-consistent register files,  instruction level parallelism,  

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High power consumption and slow access of enlarged and multiported register files make it difficult to design high performance superscalar processors. The clustered architecture, where the conventional monolithic register file is partitioned into several smaller register files, is expect to overcome the register file issues. In the clustered architecture, the more a monolithic register file is partitioned, the lower power and faster access register files can be realized. However, the partitioning causes losses of IPC (instructions per clock cycle) due to communication among register files. Therefore, degree of partitioning has a strong impact on the trade-off between power consumption and performance. In addition, the organization of partitioned register files also affects the trade-off. In this paper, we attempt to investigate appropriate degrees of partitioning and organizations of partitioned register files in a clustered architecture to assess the trade-off. From the results of execute-driven simulation, we find that the organization of register files and the degree of partitioning have a strong impact on the IPC, and the configuration with non-consistent register files can make use of the partitioned resources more effectively. From the results of register file access time and energy modeling, we find that the configurations with the highly partitioned non-consistent register file organization can receive benefit of the partitioning in terms of operating frequency and access energy of register files. Further, we examine relationship between IPS (instructions per second) and the product of IPC and operating frequency of register files. The results suggest that highly partitioned non-consistent configurations tends to gain more advantage in performance and power.

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