A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition

Yong KIM  Hong JEONG  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E90-D   No.2   pp.562-568
Publication Date: 2007/02/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e90-d.2.562
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Speech and Hearing
Keyword: 
speech recognition,  hidden Markov model (HMM),  two-level dynamic programming (TLDP),  FPGA,  

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Summary: 
In this paper, we present an efficient architecture for connected word recognition that can be implemented with field programmable gate array (FPGA). The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the absence of multiplications to increase computational speed by reducing propagation delays. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33 MHz.