Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures

Jinhwan KIM  Jeonghun CHO  Tag Gon KIM  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E90-D   No.12   pp.1977-1985
Publication Date: 2007/12/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e90-d.12.1977
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
temporal partitioning,  reconfigurable architecture,  partial reconfiguration,  dynamic reconfiguration,  run-time reconfiguration and high-level synthesis,  

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Summary: 
In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.