Evaluation of Digitally Controlled PLL by Clock-Period Comparison

Yukinobu MAKIHARA  Masayuki IKEBE  Eiichi SANO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.6   pp.1307-1310
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1307
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
digitally controlled PLL,  clock-period comparator,  loop characteristic,  loop filter,  

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Summary: 
For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.