Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver

Takeshi KUBOKI  Akira TSUCHIYA  Hidetoshi ONODERA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.6   pp.1274-1281
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1274
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
on-chip signaling,  current-mode logic,  

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Summary: 
This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.