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A SecondOrder Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm
Hao SAN Yoshitaka JINGU Hiroki WADA Hiroyuki HAGIWARA Akira HAYAKAWA Haruo KOBAYASHI Tatsuji MATSUURA Kouichi YAHAGI Junya KUDOH Hideo NAKANE Masao HOTTA Toshiro TSUKADA Koichiro MASHIKO Atsushi WADA
Publication
IEICE TRANSACTIONS on Electronics
Vol.E90C
No.6
pp.11811188 Publication Date: 2007/06/01 Online ISSN: 17451353
DOI: 10.1093/ietele/e90c.6.1181 Print ISSN: 09168516 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: complex bandpass ΔΣAD modulator, I, Q path mismatches, dynamic matching, miltibit, dataweighted averaging,
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Summary:
We have designed, fabricated and measured a secondorder multibit switchedcapacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two ninelevel quantizers and four DACs are used in the modulator for lowpower implementations and higher signaltonoiseanddistortion (SNDR), but the nonlinearities of DACs are not noiseshaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass dataweighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm^{2}. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to lowIF receivers in wireless communication systems.

