Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Atsushi IWATA  Takeshi YOSHIDA  Mamoru SASAKI  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.6   pp.1149-1155
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1149
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
low-noise amplifier,  autozeroing,  chopper stabilization,  switched op-amp,  VCO,  ring oscillator,  

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Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.