Challenges in Designing CMOS Wireless Systems-on-a-Chip

Masoud ZARGARI  David SU  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.6   pp.1142-1148
Publication Date: 2007/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.6.1142
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
wireless system on-a-chip (SoC),  RF CMOS,  wireless LAN (WLAN) transceivers,  IEEE 802.11b/g,  low-noise amplifiers (LNAs),  power amplifiers (PAs),  

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Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip. This paper describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, mixers, and frequency synthesizers. System-on-a-chip integration issues such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.