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Two-Dimensional Simulation of Electric Field and Carrier Concentration of Low-Temperature N-Channel Poly-Si LDD TFTs
IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Junction Formation and TFT Reliability
n-channel poly-Si LDD TFT, device simulation, electric field distribution, carrier concentration distribution, hot-carrier degradation,
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A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg<Vd) in LDD TFT, the maximum 2-D lateral electric field is in the deep region under the gate edge, and the current flows in the deep channel region near the drain junction. These results suggest that the drain avalanche hot-carrier (DAHC) degradation first occurs at both the gate oxide/poly-Si and poly-Si/substrate interfaces and grain boundaries in deep LDD region under the gate edge due to the state generation. In the weak current saturation bias (Vg=Vd), weak channel pinch-off occurs near the channel/LDD junction and degradation due to hot-electron injection into the gate oxide under the gate will occur in the LDD region.