Design and Simulation of Asymmetric MOSFETs

Jong Pil KIM  Woo Young CHOI  Jae Young SONG  Seongjae CHO  Sang Wan KIM  Jong Duk LEE  Byung-Gook PARK  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.5   pp.978-982
Publication Date: 2007/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.5.978
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Junction Formation and TFT Reliability
asymmetric MOSFET,  LDD,  mesa structure,  sidewall spacer gate,  

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A novel asymmetric MOSFET with no LDD on the source side is simulated on bulk-Si using a device simulator (SILVACO). In order to overcome the problems of the conventional asymmetric process, a novel asymmetric MOSFET using mesa structure and sidewall spacer gate is proposed which provides self-alignment process, aggressive scaling, and uniformity. First of all, we have simulated to compare the characteristics between asymmetric and symmetric MOSFETs. Basically, both asymmetric and symmetric MOSFETs have an n-type channel (25-nm) and the same physical parameters. When we compare this with the 25-nm symmetric MOSFET, the proposed asymmetric MOSFET shows better device performances.