A Novel Power MOSFET Structure with Shallow Junction Dual Well Design

Chien-Nan LIAO  Feng-Tso CHIEN  Chi-Ling WANG  Hsien-Chin CHIU  Yi-Jen CHAN  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.5   pp.937-942
Publication Date: 2007/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.5.937
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Compound Semiconductor and Power Devices
power VDMOSFET,  shallow dual well,  gate charge,  avalanche breakdown,  

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Vertical Power MOSFETs are widely designed by deep well structures for breakdown requirement. In this study, we proposed, simulated, and analyzed a "shallow dual well" structure Power MOSFET, which utilize an n-well to cover the conventional p-well. The cell pitch can be reduced and results in an increased cell density. The reduced cell pitch and increased cell density improves the gate charge and on resistance performances about 66.5% and 15.8% without sacrificing the device breakdown owing to a shallow junction design. In addition, with the dual well structure design, the breakdown point will occur at the center of the well. Therefore, the capability of avalanche energy can be improved about 1.9 times than the tradition well structure.