Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation

Noriaki ODA  Hironori IMURA  Naoyoshi KAWAHARA  Masayoshi TAGAMI  Hiroyuki KUNISHIMA  Shuji SONE  Sadayuki OHNISHI  Kenta YAMADA  Yumi KAKUHARA  Makoto SEKINE  Yoshihiro HAYASHI  Kazuyoshi UENO  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.4   pp.848-855
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.848
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Device
copper,  low-k,  CMOS,  interconnect,  design,  application,  

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A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.