18-GHz Clock Distribution Using a Coupled VCO Array

Takayuki SHIBASAKI  Hirotaka TAMURA  Kouichi KANDA  Hisakatsu YAMAGUCHI  Junji OGAWA  Tadahiro KURODA  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.4   pp.811-822
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.811
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Analog and Communications
high-speed I/O,  clock distribution,  oscillators,  injection locking,  voltage-controlled oscillator,  

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This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.