Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS


IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.4   pp.779-785
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.779
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
analog circuits,  integrated circuits,  analog-to-digital converter,  CMOS,  low-power operation,  low-voltage operation,  technology scaling,  

Full Text: PDF(705.5KB)>>
Buy this Article

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.